Process for forming metalized contacts to periphery transistors



A process and apparatus directed to forming metal plugs (75,76,95,96) in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions (25,26) of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into theactive areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.




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